ISL6112INZA-T【PDF 19/30 页】IC PWR CNTRLR DUAL SLT 48-TQFP

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ISL6112

FN6456.1

August 25, 2011

Start bit must then be sent to the ISL6112, followed by a repeat

of the device address, with the R/W

bit set to the high (read)

state. The data to be read from the part may then be clocked out.

The exception to this rule is that, if the location latched in the

pointer register from the last write operation is known to be

correct (i.e., points to the desired register within the ISL6112),

the Receive_Byte procedure may be used. To perform a

Receive_Byte operation, the host sends an address byte to select

the target ISL6112, with the R/W

bit set to the high (read) state,

and then retrieves the data byte. Figures 33, 34 and 35 show the

formats for these data read and data write procedures.

The Command Register is eight bits (one byte) wide. This byte

carries the address of the ISL6112 register to be operated upon.

Command byte values corresponding to the ISL6112 register

addresses are shown in Table 4. Command byte values other than

0000 0XXX

= 00

are reserved and should not be used.

ISL6112 SMBus Address Configuration

The ISL6112 responds to its own unique SMBus address, which

is assigned using A2, A1, and A0. These represent the three

Least Significant Bits (LSB) of its 7-bit address, as shown in

Table3. These address bits are assigned only during power-up of

the VSTBY supply input. These address bits allow up to eight

ISL6112 devices in a single system. These pins are either

grounded or left unconnected to specify a logical 0 or logical 1,

respectively. A pin designated as a logical 1 may also be pulled

up to VSTBY.

TABLE 3. ISL6112 SMBUS ADDRESSING

INPUTS

ISL6112 DEVICE ADDRESS

BINARY

HEX

0 1000 000X*b

80h

1 1000 001Xb

82h

0 1000 010Xb

84h

1 1000 011Xb

86h

0 1000 100Xb

88h

1 1000 101Xb

8Ah

0 1000 110Xb

8Ch

1 1000 111Xb

8Eh

* Where X = 1 for READ and 0 for WRITE

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